1. Circuit diagram

shift register : With storage code , Shift function
displacement : The code stored in the register can be under the action of shift pulse , Move left or right in turn
2.VHDL language
2.1 D trigger
library ieee; use ieee.std_logic_1164.all; entity dff1 is port( clk,d:in
std_logic; q:out std_logic ); end dff1; architecture behavior of dff1 is begin
process(clk) -- Process statements and sensitive signals begin if rising_edge(clk) then q <= d; --rising_edge
Is a very strict rising edge , Must from 0 reach 1 end if; end process; end behavior;
2.2 4 Shift bit register
describe 1
library ieee; use ieee.std_logic_1164.all; entity shift_reg is port (a,clk :
in std_logic; b : out std_logic); end shift_reg; architecture behave of
shift_reg is component dffport(d,clk:in std_logic; q:out std_logic); end
component; signal z:std_logic_vector(0 to 4); begin dff1:dff port map(a,clk,z(1)
); dff2:dff port map(z(1),clk,z(2)); dff3:dff port map(z(2),clk,z(3)); dff4:dff
portmap(z(3),clk,b); end behave;
describe 2
begin z(0)<=a;b<=z(4); dff1:dff port map(z(0),clk,z(1)); dff2:dff port map(z(1)
,clk,z(2)); dff3:dff port map(z(2),clk,z(3)); dff4:dff port map(z(3),clk,z(4));
end behave;
describe 3
begin z(0)<=a;b<=z(4); g1:for i in 0 to 3 generate --for generate sentence dffx:dff
portmap(z(i),clk,z(i+1)); end generate; end behave;

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