1. brief introduction

1. In the process of digital circuit design , It is often necessary to divide the clock signal with higher frequency , Thus, a lower frequency clock signal is obtained .
A hardware circuit , If the clock signal is not designed correctly , It will lead to the failure of the whole hardware circuit design .
2. Frequency divider ： Complete the of clock signal 2 frequency division ,4 frequency division ,8 Frequency division sum 16 frequency division

2. Design of frequency divider
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use
ieee.std_logic_unsigned.all; entity clk_2468 is port(clk : in std_logic;
clk_div2,clk_div4,clk_div8,clk_div16 : out std_logic); end clk_2468;
architecture behave of clk_2468 is signal count: std_logic_vector(3 downto 0);
beginprocess(clk) begin if(clk'event and clk = '1') then if(count = "1111")
then count<= (others => '0'); else count <= count + 1; end if; end if; end
process; clk_div2 <= count(0); clk_div4 <= count(1); clk_div8 <= count(2);
clk_div16<= count(3); end behave;

3. Even multiplexer （8 frequency division ）
library ieee; use ieee.std_logic_1164.all; entity divider_8 is port(clk : in
std_logic; oul : out std_logic); end divider_8; architecture behave of
divider_8 is constant n: integer := 3; signal counter : integer range 0 to n;
signal s1: std_logic; begin process(clk) begin if rising_edge(clk) then -- Strict rising edge
if counter = n then counter <= 0; -- Every four rising edges ,counter Just clear s1 <= not s1; --s1 Just reverse （0 And 1）
else counter <= counter + 1; end if; end if; end process; oul <= s1; end behave;

4. The duty cycle is 1:15 of 16 Frequency divider
library ieee; use ieee.std_logic_1164.all; entity div1_15 is port(clk : in
std_logic; clk_div16 : out std_logic); end div1_15; architecture behave of
div1_15 is signal count: std_logic_vector(3 downto 0); begin process(clk) begin
if(clk'event and clk = '1') then if(count = "1111") then clk_div16 <= '1'; else
clk_div16<= '0'; end if; end if; end process; end behave;

5. Odd multiple divider （3 frequency division ）
library ieee; use ieee.std_logic_1164.all; entity divider_3 is port(clock : in
std_logic; clk : out std_logic); end divider_3; architecture behave of
divider_3 is constant n: integer := 2; signal counter : integer range 0 to n;
signal temp1: std_logic; signal temp2 : std_logic; begin process(clock) begin if
rising_edge(clock) then if counter = n then counter <= 0; temp1 <= not temp1;
else counter <= counter + 1; end if; end if; if falling_edge(clock) then if
counter= 2 then temp2 <= not temp2; end if; end if; end process; clk <= temp1
xor temp2; end behave;

Technology
Daily Recommendation
views 1