library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use
ieee.std_logic_unsigned.all; --------------------------------------------------
------------------ entity counter is port( clk,ret,en : in std_logic; --
Define clock , Asynchronous reset , Synchronization enable signal cq: out std_logic_vector(3 downto 0); -- Counting result cout : out
std_logic-- Carry signal ); end counter; ------------------------------------------------
-------------------- architecture behave of counter is begin process(clk,ret,en)
variable cqi: std_logic_vector(3 downto 0); begin if ret='0' then cqi:= "0000";
-- Counter asynchronous reset elsif clk'event and clk='1' then-- Detect the rising edge of the clock if en='1' then--
Detect whether counting is allowed ( Synchronous enable )if cqi<15 then cqi:=cqi+1; else cqi:= "0000"; end if; end if; end
if; if cqi>9 then cout<='1';-- Output carry signal else cout<='0'; end if; cq<=cqi;-- The count value is output to the port
end process; end behave;

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