<> Applied position ：
Huawei logic （FPGA）
<> Preparation before interview ：
Basic part of digital circuit ,FPGA Common interview questions （ synchronization , asynchronous , Metastable state , Cross clock domain ,FPGA Internal logic , Timing constraints and other common problems ）, Familiar with personal projects （ Must be very careful review !）, I started preparing a month in advance .
<> written examination （ End of August ）：
Huawei's written test mainly focuses on some basic knowledge of data and electricity ,Verilog Basic knowledge ,FPGA Common basic knowledge in English , a few C Language and modeling problems , The overall problem is not difficult , It's easier to pass .
<> one side （ Professional interview ）（ September 3 day ）：
One side takes a long time , Mainly asked about the academic performance , Why is the result not better （ Because I was stupid to death , Fill in the top percent 50, Before actual 30% about , However, there is no such choice for filling in a resume , I didn't answer very well in the interview ）, And then for SDRAM The controller project asked a lot of questions, including ：SDRAM Why refresh ? Data bit width ? Maximum operating frequency ? Drawing system block diagram ? Describe arbitration priority ? Minimum read write interval TRC How much is it ? How to write ? What is the efficiency of reading and writing （ I didn't answer that , It's not measured ）? There are still many things I can't remember clearly , Anyway, the question is very detailed , I have asked all the key questions . Then the basic problem ： use D The trigger draws a binary frequency ? use Verilog Write an asynchronous reset ? Synchronous reset 17 Decimal counter ?FPGA The internal structure of ? Chips and platforms used ? block RAM Capacity of ? Is it a whole ? Some of them are not very clear , Finally, I asked what I wanted to ask him ? After the interview, the interviewer said I had , Then prepare for the next one .（ On the one hand, the overall problem is not difficult , The comparative basis of questions , But the question is very detailed , Mainly according to the project , I just asked SDRAM Controller is a project , From beginning to end , I was well prepared before , Basically all the questions were answered , Only the reading and writing efficiency has not been tested ）
<> Two sides （ Professional interview ）（ September 3 day ）：
I thought it would be more difficult for two sides , Introduce yourself first , Then ask what is the biggest problem in the project , How to solve it ? And then they started asking questions SDRAM The question of , I feel I have nothing to ask , Let me write a rising edge detection code , Every time 10 A rising edge produces a flag bit output , After writing and uploading , I'm told it's over , Prepare for three .
<> Three sides （ Business management ）（ September 3 day ）：
Business management , The interviewer was very serious when he came up , Let me introduce myself , And then I started asking again SDRAM The question of , And the difficulty of the problem has increased , I was asked about the efficiency of reading and writing （ Notice here , If there's a question ahead that hasn't been answered , You'd better get to know it after the interview , To avoid being asked again ） Of course, I didn't answer ,SDRAM What are the main design difficulties ? When the refresh request comes , When the read data is in burst mode , Data not burst out , Here comes the refresh request , If you wait for a burst to complete, the refresh request may not get timely response , What should we do at this time （ A burst if interrupted , It will result in the loss of data that needs to be read and written later , So generally waiting for the end of the burst in the jump out of the current state ）? Then he asked again FPGA The internal composition of ?LE The realization principle of look up table in ? Distributed RAM And block RAM What's the difference? ? How do look-up tables and triggers form a distributed system RAM Of ? The difference between global clock domain and local clock ?IOB The main components of ? What are the reasons for the unsatisfied setup time and the unsatisfied retention time , How to solve it , How to do it ? Then the interviewer starts to talk about home , What do you know about Huawei （ I'm going to recite the history of Huawei , Just after a while, the interviewer laughed , Say no, no, No , Just say how you feel , This scene is so interesting ）? Where do you live ? Where's your position ? It's said that Huawei's overtime work is too serious , The wind comment is not good or something , Ask me what I think ? Ask me what hobbies I have ( I like running , Then ask 10 Kilometer results , Half horse results , Then the interviewer likes to run, too , Half a horse , Then I was shocked by my pace )? And then it's almost over on three sides , Finally, do I have anything to ask him ? I asked some questions about when the results would come out , And will there be any training after entering the company ? The interviewer told me about the training in detail , I can learn a lot . And then the three sides are over , After a while, I received a text message from three sides .
<> Personal feelings ：
Three times in a row in the afternoon , It took more than four hours , Generally speaking, most of the interview questions of Huawei logic are not difficult , The project is very detailed , Professional questions are routine interview questions , about FPGA Internal resources , There are many questions about internal structure and other related knowledge , Pay more attention to the foundation . The overall feeling of the three rounds of interviews was pretty good , Maybe the answers to some questions on the third side are not so comprehensive , Have you ever been asked about your grades , And undergraduate schools , My undergraduate school is not very good , There are also some problems in filling in the postgraduate scores , Only before 25% After that is the front 50% Options for , I feel bad, too ! The actual results are the best 30% But I didn't get the choice , Make it clear to the interviewer first , In the third interview, I asked if it was before 50%, I didn't explain my actual ranking . I feel that this may be the main reason why I am stuck .
<> period 10 month 9 Sunday comfort call ,11 Monthly comfort call
<>11 month 4 day OD
<>12 month 3 Rijiamian
<>12 month 4 Received letter of intent and employment agreement from Huawei !!! Successful acquisition of Huawei offer, The salary is also very satisfactory, higher than expected 2k, It's worth the wait !!!