stay Linux Environment , We complete the compilation of a file , Just one gcc 
[filename] Your orders ; however , When we are compiling a project , If you still want to use a command to complete the compilation of the whole project , Only with the help of makefile, To do it “ Automatic compilation ”;

makefile/Makefile Store our own compilation rules ; and make It's an explanation makefile Command tools for commands in

makefile Rules of writing :

Target object : Dependent object

  Compile command

eg: We have one test.c file , Compile to generate executable file test, ours makefile The code is as follows :

test:test.c                       // Target object ( Executable file test): Dependent object ( source file test.c)

gcc -c test.c -o test      // Compile command ( Compilation Rules )

If we have multiple dependent objects, such as test.c  add.c sub.c etc. , At this time, our makefile It should be as follows

test:test.c add.c sub.c

gcc -c test.c  add.c sub.c -o test  

Predefined variables :

As if we have defined the target object and dependent object above , So we can use the makefile Predefined variables :

^@ Represents the target object    

 ^$ Represents all dependent objects that generate the target object  

^< Represents the first dependent object

above makefile We can rewrite it as

test:test.c add.c sub.c

gcc -c ^$ -o ^@ -g           ( If we want the executable program to be debuggable , Namely Debug edition , You need to add -g option )  

Custom variable :

We know three things about it makefile Predefined variables for , In fact makefile in , We can also customize variables

But when using custom variables , We need to use variables when we need to use them $()

With the above makefile take as an example

SRC=test.c  add.c sub.c 
 // Custom variable SRC Representation generation test Required dependent objects , The benefits of using variables are , When you need to change the dependent object later , We just need to make changes when we define variables , More convenient

test:$(SRC)

gcc -c $(SRC)  -o  test  

$() Except for using variables , You can also refer to shell command  , Gets the result of the command

$(shell mkdir include)     // Create a include folder

PATH=$(shell pwd)       // Save the current directory in PATH In variable

function :

wildcard:

The function is called as an existing function , Separated by spaces , List of all files that match this pattern

  Usually with wildcards ;

eg:SRCS=$(wildcard *.c)

Add all the .c File assigned to variable SRCS

If we have add.h  add.c  main.c Three documents

The command on this side corresponds to SRCS=add.c  main.c

addprefix:

This function is used to add a prefix

eg:

BIN=main               // A variable is defined BIN, Used to save the execution file

BUILD_ROOT=/root/work   // A variable is defined , Used to save the path

BIN := $(addprefix $(BUILD_ROOT)/, $(BIN))  // Add path to executable file

//BIN=/root/work/main

Symbol :

@ : Means in make At the time of execution , In the output information , Do not display this command line

-   : If the current line is executed , An error occurred , Then ignore

notes :

For others or yourself to be able to quickly understand in the future , Written by makefile, Annotations are essential

makefile In the file "#" Character is the beginning of a comment , It's equivalent to C Linguistic " // "

eg:

# A variable is defined BIN, Used to save the execution file

BIN=main               

# A variable is defined , Used to save the path

BUILD_ROOT=/root/work   

# Add path to executable file     BIN=/root/work/main

BIN := $(addprefix $(BUILD_ROOT)/, $(BIN)) 

  Include other makefile

In a project , We must have multiple directories , Store different files ; Under each directory , We're all likely to write one makefile, Take these makefile Link up , It's a very important thing ;

Finish it , We are bound to meet an old friend include , We're using it include Include the rest makefile When I was young , It's better to add the path , Make sure it's found

eg:

BUILD_ROOT=/root/work   

include $(BUILD_ROOT)/common.mk

 

  notes : If there are any mistakes and suggestions in this blog , Welcome to leave a message , You have to say something !

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