1.管脚图

2.真值表

3.VHDL语言
library ieee; use ieee.std_logic_1164.all; entity jkff is port(j,k,clk : in
std_logic; q,nq : out std_logic); end jkff; architecture behave of jkff is
signal q_s,nq_s : std_logic; begin process(clk,j,k) begin if(clk'event and clk
= '1') then if(j = '0') and (k = '1') then q_s <= '0'; nq_s <= '1'; elsif(j =
'1') and (k = '0') then q_s <= '1'; nq_s <= '0'; elsif(j = '1') and (k = '1')
then q_s<= not q_s; nq_s <= not nq_s; end if; end if; q <= q_s; nq <= nq_s; end
process; end behave;

技术
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